This project presents a comparative analysis of 6T, 7T, and 8T SRAM cell architectures implemented using 90nm CMOS technology, with a focus on optimizing memory performance for modern VLSI systems. By evaluating key parameters such as power consumption, area efficiency, read/write stability, and leakage currents, the study aims to identify trade-offs and advantages inherent in each design. The 6T cell, widely adopted for its compactness, is contrasted with the 7T and 8T variants that introduce additional transistors to enhance data stability and reduce dynamic power. Simulation results using Cadence Virtuoso provide insight into how each topology behaves under scaled voltage and process variations. The findings offer valuable guidance for designers seeking to balance speed, reliability, and silicon real estate in SRAM-intensive applications.

References:
[1] A. Jaiswal, I. Chakraborty, A. Agrawal and K. Roy, "8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2556-2567, Nov. 2019, doi: 10.1109/TVLSI.2019.2929245.