This project presents the design and implementation of a smart washing machine controller tailored for modern automated laundry systems. The controller manages key operational states—check, fill water, add detergent, cycle, drain, and spin—across two distinct modes: water wash and soap wash, each with its own flow logic. At its core lies a finite state machine (FSM) that interprets inputs from users, timers, and sensors to control hardware components. The RTL design was developed using Verilog HDL in Quartus, followed by simulation through a dedicated testbench. Synthesis was performed using Genus, yielding a schematic and power metrics including a total power of 1.05 × 10⁻². The IC layout was crafted in Innovus with proper constraints and cell placements. Static timing analysis (STA) reports were generated and violations resolved both before and after clock tree synthesis and routing. Final physical verification ensured compliance through DRC, geometry, connectivity, and ARC checks. This comprehensive flow demonstrates a robust and efficient embedded system for smart appliance control.